1. Field of the Invention
The present invention relates to a method for forming metal wires of a semiconductor device, and particularly to a method for forming metal wires of very-large-scale integration (VLSI) semiconductor devices having metal wire pitches at submicron dimensions.
2. Description of Related Art
Recent developments in miniaturization techniques at submicron dimensions have facilitated rapid and remarkable increases in the integration density of semiconductor memory devices. For example, 4 Mbit DRAMs of 0.8 micron design scale are now in manufacture. 16 Mbit DRAMS of similar design scale are also about to be mass produced. In addition, 64 Mbit and 256 Mbit DRAMS of 0.5 micron design scale are presently under active study. These advanced designs in VLSI semiconductor memory devices require the use of multiple metal layering process for forming metal wires.
Conventionally, metal wires are produced by the following general steps: introducing contact holes on the surface of a material covering a semiconductor; body forming metal wires; and covering the surface of the semiconductor body with a passivation film.
FIGS. 1A-1D are cross-sectional structural diagrams of a semiconductor device at various stages in the above-described process. Inter-insulating layer 2 is layered to cover semiconductor substrate 1. Next, contact hole 3 is created in inter-insulating layer 2. Subsequently, barrier layer 4, made of a refractory metal such as an aluminum or aluminum alloy, is blanketed over the entire surface of layer 2. Next, metal layer 5 is deposited over barrier layer 4 a by sputtering or chemical vapor deposition (CVD) method. A photoresist is placed over metal layer 5, following which photoresist pattern 6 is formed via photolithography. Metal wires 7 in FIG. IC are then formed by etching metal layer 5 and barrier layer 4, using photoresist pattern 6 as a mask. Subsequently, as illustrated in FIG. ID, the resulting structure is coated with passivation film 8, which may consist of material such as phosphor-silicate glass (PSG) or borophosphorous-silicate glass (BPSG).
In the above procedure, metal layer 5 is etched via lithography to form metal wires prior to being coated with passivation film 8. This implies that as the distance between two adjacent metal wires 7 is narrowed (e. g., to submicron dimensions), the aspect ratio of the groove between two adjacent metal wires becomes larger. Thus, the narrowing of the grooves leads to creation of voids 23 during the coating of passivation film 8. In addition, the surface of passivation film 8 becomes rough and uneven because of "stepped" structure of metal wires 7. The uneven surface of passivation film 8 and voids 23 decrease the robustness of metal wires 7 and renders the subsequent processing of semiconductor devices difficult. The defects may even cause disconnections of or short between metal wires.